1. Field of the Invention
The present invention relates to a semiconductor substrate having a plurality of semiconductor elements arrayed and implemented thereon in a manufacturing process of a semiconductor device, and a method for manufacturing a semiconductor device using the semiconductor substrate.
2. Description of the Related Art
In recent years, the requirement has arisen for semiconductor device (hereinafter referred to as a semiconductor package) is required to be miniaturized so that they can be mounted on a small electronic equipment such as a portable telephone. For this reason, in a BGA (Ball Grid Array) type of a semiconductor package, miniaturizing the semiconductor package is proceeded by making a wiring board having a semiconductor element (hereinafter referred to as a semiconductor chip) that is to be mounted thereon smaller.
Thus, a semiconductor package which is formed into a size approximately equal to that of the semiconductor chip can be practically used. As a result, the area occupied by the semiconductor chip in the wiring board has been increasing. Along with the increase, dimensional tolerance required in the manufacturing process of the semiconductor package has become much severer. Generally, the progress for manufacturing a semiconductor package includes a step of dicing the substrate, which is the step of cutting the semiconductor substrate, on which a plurality of the semiconductor chips have been implemented, along a dividing line (hereinafter referred to as dicing line) into individual semiconductor packages and separating them. Accordingly, it has become necessary to enhance the accuracy of the dicing position of the wiring board.
Such a process of dicing a substrate includes: firstly detecting the position of a semiconductor substrate by making a recognition camera that has a comparatively low magnification and a wide field of view recognize a large recognition mark which is arranged in four corners of the semiconductor substrate and which can be comparatively easily detected; subsequently detecting the position of a dicing line by making the recognition camera which has retained the magnification, as is, recognize a pattern shape that configures the recognition mark arranged on each dicing line; and finally dicing the semiconductor substrate while referring to the position of the detected dicing line. The method uses a recognition camera of low magnification when making the camera recognize the position of the dicing line by using the recognition mark. Therefore, the accuracy in the method is shown to be inferior to the processing accuracy in a process of dicing wafers when a recognition camera that has high magnification is caused to recognize the dicing position.
In addition, a technology for dicing the semiconductor substrate in relation to the present invention is disclosed in Japanese Patent Laid-Open No. 2002-246336 (FIG. 2). In this patent publication, the wiring board has recognition marks that have a rectangle of 0.3 mm×0.5 mm arranged on lines that extend from the dicing lines for cutting the substrate into individual semiconductor packages in the perimeter of the wiring board. The patent publication also discloses a method for dicing the wiring board through recognizing the position of the dicing line while referring to the two recognition marks in positions that face each other.
By the way, as was described above, the recognition mark provided on the wiring board is formed by an etching technique or the like simultaneously with the formation of the wiring pattern which will become a product. For this reason, when the wiring pattern is etched in the process of manufacturing the wiring board, a so-called sag is formed which means that a broken shape in one part of the perimeter of the pattern shape that configures the recognition mark occurs due to dissolution by an etchant. Such a sag in the pattern shape is more remarkable when the wiring pattern formed in the wiring board is made more microscopic. Accordingly, it is difficult to make a shape having a fine pattern shape with such accuracy that the pattern center can be stably detected.
When the sag is formed in the pattern shape configuring the recognition mark, the camera cannot stably recognize the position of the pattern center, which causes the misalignment of the dicing position of the wiring board. When the misalignment of the dicing position has occurred, the wiring pattern of the wiring board and a wire for electrically connecting the wiring board with the semiconductor chip may be cut.
In addition, in the process of dicing the substrate, it is desirable that the pattern shape that configures the recognition mark that causes a dicing device to recognize the dicing position be a characteristic shape so as to make the dicing device easily detect the recognition mark, and it is desirable that the pattern shape have a symmetric shape so as to enable the dicing device to have sufficient accuracy. It is also thought that the pattern shape that configures the recognition mark should be into a fine shape in order to achieve further accurate recognition with the use of a recognition camera having high magnification and a narrow field of view. However, when the recognition mark is formed to have a fine pattern shape in the step of forming the wiring pattern on the substrate, the pattern shape in the recognition mark will vary and consequently becomes unusable as the pattern shape. Then, it is difficult to employ a method of detecting the position by using a recognition camera having high magnification in the step of dicing the substrate, and accordingly it is necessary to secure large dimensional tolerance, which prevents miniaturization of the semiconductor package.
The recognition mark disclosed in the above described Patent document 1 has a problem in which the a corner part of the pattern shape which is formed into a rectangle is dissolved in the etchant which causes the pattern shape to easily break which causes the recognition mark be barely detectable. In addition, the pattern shape of the recognition mark is formed into a rectangle which is similar to the wiring pattern formed on the wiring board, which causes a problem that one part of the wiring pattern is easy to be wrongly recognized as the recognition pattern.